The present invention relates to a method and apparatus for verifying semiconductor integrated circuits.
The development of semiconductor integrated circuits includes the process of calculating delays in a logic circuit and verifying operation timings and delays in the logic circuit to check and ensure proper operation of the logic circuit. In recent years, semiconductor integrated circuits have a higher level of integration and operate at higher speeds and lower operation voltages. In such semiconductor integrated circuits, variations in power supply voltage drops within chips greatly affect delays and fluctuations in circuit operations. Thus, static timing analysis (STA) must be executed by taking into consideration such differences.
When designing a semiconductor integrated circuit in the prior art, a netlist is first generated through logical synthesis, and then a chip layout is generated based on the netlist. The STA is executed based on the layout result.
FIG. 1 is a flowchart showing a timing verification process in the prior art. This process is executed by a verification apparatus (not shown).
First, the verification apparatus estimates variations in the power supply voltage drop of a chip-shaped semiconductor integrated circuit (step 101), extracts the parasitic capacitance of the circuit based on the layout of the semiconductor integrated circuit (the arrangement and wiring of instances (cells)) (step 102), and calculates a delay value (step 103). Next, the verification apparatus executes a path analysis to extract a data path and a clock path (step 104) and then executes a pulse width check (step 105) and a timing check (step 106) for each path using the delay value. Then, the verification apparatus determines the appropriateness of the layout based on the results of these checks (step 107).
Variations in processes for forming transistors and wires in semiconductor integrated circuits and variations in power supply voltages and temperatures of semiconductor integrated circuits affect the delay time of cells included in semiconductor integrated circuits. Therefore, the verification apparatus estimates the amount of variation of these variation factors. The verification apparatus then expresses the influence of each variation factor on delays as an on-chip variation coefficient (OCV coefficient), based on the estimated variation amount. The verification apparatus multiplies a delay value by the OCV coefficient to obtain a delay value taking on-chip variations into consideration. The verification apparatus executes the timing check and the pulse width check using the calculated delay value.
For example, as shown in FIG. 2(a), a chip-shaped semiconductor integrated circuit includes a flip flop circuit 112, which receives a clock signal CK via plural stages of buffer circuits 111. In the pulse width check, the pulse width of the clock signal CK at a clock input terminal 112a of the flip flop circuit 112 is checked. The clock signal CK is subjected to a path delay by the plural stages of buffer circuits 111 and reaches the flip flop circuit 112 as a clock signal CKn having the path delay. The pulse width PWn of the clock signal CKn is calculated using the pulse width PWH of the clock signal CK and a rise delay time PR and a fall delay time PF between the source of the clock signal CK (e.g., an external input terminal) and an input terminal of a buffer circuit 111. In short, the pulse width PWn is calculated using the expression PWn=PWH+PF−PR.
The rise delay time PR is the delay time of the rising edge of the clock signal CKn with respect to the rising edge of the clock signal CK. The fall delay time PF is the delay time of the falling edge of the clock signal CKn with respect to the falling edge of the clock signal CK. In this case, the maximum value of rise delay times considering delay variations is used as the rise delay time PR, and the minimum value of fall delay times considering delay variations is used as the fall delay time PF. In the prior art, the pulse width check is executed by comparing the pulse width PWn calculated using the above expression with a standard value tPW of a target cell (the flip flop circuit 112 in this case). The rise delay time PR is set at its maximum value and the fall delay time PF is set at its minimum value so that the pulse width check is executed under a harsh condition in which the difference between the rise delay time PR and the fall delay time PF is large.
Japanese Laid-Open Patent Publication No. 2001-184372 discloses a method for verifying pulse width using the above expression. For example, as shown in FIG. 3(a), a semiconductor integrated circuit includes two flip flop circuits 113 and 114. In this case, the timings of a data signal (Data) and a clock signal (CK), which are respectively provided to input terminals 114a and 114b of the flip flop circuit 114, are checked. In the timing check considering on-chip variations, strict checking is performed taking into consideration delay variations of one of the data signal (Data) and the clock signal (CK).